TLB Performance in Multiprocessors by Patricia

This paper compares the performance, in highly-parallel shared-memory multiprocessors, of locating translation-lookaside buffers (TLBs) at processors with that of locating TLBs at memory. Our performance comparison is based on results of trace-driven simulations of multiprocessors with logN-stage networks interconnecting N processors and N memory modules. For the systems and workloads studied, memory-based TLBs perform better than processor-based TLBs, provided that memory is organized as multiple paging arenas, where the mapping of pages to arenas is fixed. The cost of a processor-based TLB reload is at least logN because of network transit. The cost of a memory-based TLB reload can be made smaller than that of a processor-based TLB reload, since network transits are not required. Furthermore, with multiple paging arenas, the number of reloads is smaller with memory-based TLBs. For memory-based TLBs to continue to outperform processor-based TLBs for large N, it is likely that the number of paging arenas must grow with N. ____________________________________ Supported by U.S. Department of Energy grant number DE-FG02-88ER25052, National Science Foundation grant number MDS-8301768, and the IBM Corporation. Supported in part by U.S. Department of Energy grant DE-FG02-88ER25052 and National Science Foundation grant number MIP-8915488.